#ifndef __REG_DWUART_TYPE_H__
#define __REG_DWUART_TYPE_H__
#include <stdint.h>

typedef struct
{
    volatile uint32_t RBR_THR_DLL;
    volatile uint32_t DLH_IER;
    volatile uint32_t IIR_FCR;
    volatile uint32_t LCR;
    volatile uint32_t MCR;
    volatile uint32_t LSR;
    volatile uint32_t MSR;
    volatile uint32_t SCR;
    volatile uint32_t LPDLL;
    volatile uint32_t LPDLH;
    volatile uint32_t reserved0[2];
    volatile uint32_t SRBR0_STHR0;
    volatile uint32_t SRBR1_STHR1;
    volatile uint32_t SRBR2_STHR2;
    volatile uint32_t SRBR3_STHR3;
    volatile uint32_t SRBR4_STHR4;
    volatile uint32_t SRBR5_STHR5;
    volatile uint32_t SRBR6_STHR6;
    volatile uint32_t SRBR7_STHR7;
    volatile uint32_t SRBR8_STHR8;
    volatile uint32_t SRBR9_STHR9;
    volatile uint32_t SRBR10_STHR10;
    volatile uint32_t SRBR11_STHR11;
    volatile uint32_t SRBR12_STHR12;
    volatile uint32_t SRBR13_STHR13;
    volatile uint32_t SRBR14_STHR14;
    volatile uint32_t SRBR15_STHR15;
    volatile uint32_t reserved1[3];
    volatile uint32_t USR;
    volatile uint32_t TFL;
    volatile uint32_t RFL;
    volatile uint32_t SRR;
    volatile uint32_t reserved2[6];
    volatile uint32_t HTX;
    volatile uint32_t DMASA;
    volatile uint32_t reserved3[5];
    volatile uint32_t DLF;
    volatile uint32_t reserved4[12];
    volatile uint32_t CPR;
    volatile uint32_t UCV;
    volatile uint32_t CTR;
} reg_dwuart_t;

enum DWUART_RBR_THR_DLL_FIELD
{
    DWUART_RBR_MSB_9THBIT_MASK = 0x100,
    DWUART_RBR_MSB_9THBIT_POS = 8,
    DWUART_RBR_LSB_8BITS_MASK = 0xff,
    DWUART_RBR_LSB_8BITS_POS = 0,
    DWUART_THR_MSB_9THBIT_MASK = 0x100,
    DWUART_THR_MSB_9THBIT_POS = 8,
    DWUART_THR_LSB_8BITS_MASK = 0xff,
    DWUART_THR_LSB_8BITS_POS = 0,
    DWUART_DIVISOR_LATCH_LOW_MASK = 0xff,
    DWUART_DIVISOR_LATCH_LOW_POS = 0,
};

enum DWUART_DLH_IER_FIELD
{
    DWUART_DIVISOR_LATCH_HIGH_MASK = 0xff,
    DWUART_DIVISOR_LATCH_HIGH_POS = 0,
    DWUART_PTIME_MASK = 0x80,
    DWUART_PTIME_POS = 7,
    DWUART_EDSSI_MASK = 0x8,
    DWUART_EDSSI_POS = 3,
    DWUART_ELSI_MASK = 0x4,
    DWUART_ELSI_POS = 2,
    DWUART_ETBEI_MASK = 0x2,
    DWUART_ETBEI_POS = 1,
    DWUART_ERBFI_MASK = 0x1,
    DWUART_ERBFI_POS = 0,
};

enum DWUART_IIR_FCR_FIELD
{
    DWUART_FIFOSE_MASK = 0xc0,
    DWUART_FIFOSE_POS = 6,
    DWUART_IID_MASK = 0xf,
    DWUART_IID_POS = 0,
    DWUART_RCVR_MASK = 0xc0,
    DWUART_RCVR_POS = 6,
    DWUART_TET_MASK = 0x30,
    DWUART_TET_POS = 4,
    DWUART_DMAM_MASK = 0x8,
    DWUART_DMAM_POS = 3,
    DWUART_XFIFOR_MASK = 0x4,
    DWUART_XFIFOR_POS = 2,
    DWUART_RFIFOR_MASK = 0x2,
    DWUART_RFIFOR_POS = 1,
    DWUART_FIFOE_MASK = 0x1,
    DWUART_FIFOE_POS = 0,
};

enum DWUART_LCR_FIELD
{
    DWUART_DLAB_MASK = 0x80,
    DWUART_DLAB_POS = 7,
    DWUART_BREAK__MASK = 0x40,
    DWUART_BREAK__POS = 6,
    DWUART_STICK_PARITY_MASK = 0x20,
    DWUART_STICK_PARITY_POS = 5,
    DWUART_EPS_MASK = 0x10,
    DWUART_EPS_POS = 4,
    DWUART_PEN_MASK = 0x8,
    DWUART_PEN_POS = 3,
    DWUART_STOP_MASK = 0x4,
    DWUART_STOP_POS = 2,
    DWUART_DLS_MASK = 0x3,
    DWUART_DLS_POS = 0,
};

enum DWUART_MCR_FIELD
{
    DWUART_SIRE_MASK = 0x40,
    DWUART_SIRE_POS = 6,
    DWUART_AFCE_MASK = 0x20,
    DWUART_AFCE_POS = 5,
    DWUART_LOOPBACK_MASK = 0x10,
    DWUART_LOOPBACK_POS = 4,
    DWUART_OUT2_MASK = 0x8,
    DWUART_OUT2_POS = 3,
    DWUART_OUT1_MASK = 0x4,
    DWUART_OUT1_POS = 2,
    DWUART_RTS_MASK = 0x2,
    DWUART_RTS_POS = 1,
    DWUART_DTR_MASK = 0x1,
    DWUART_DTR_POS = 0,
};

enum DWUART_LSR_FIELD
{
    DWUART_ADDR_RCVD_MASK = 0x100,
    DWUART_ADDR_RCVD_POS = 8,
    DWUART_RFE_MASK = 0x80,
    DWUART_RFE_POS = 7,
    DWUART_TEMT_MASK = 0x40,
    DWUART_TEMT_POS = 6,
    DWUART_THRE_MASK = 0x20,
    DWUART_THRE_POS = 5,
    DWUART_BI_MASK = 0x10,
    DWUART_BI_POS = 4,
    DWUART_FE_MASK = 0x8,
    DWUART_FE_POS = 3,
    DWUART_PE_MASK = 0x4,
    DWUART_PE_POS = 2,
    DWUART_OE_MASK = 0x2,
    DWUART_OE_POS = 1,
    DWUART_DR_MASK = 0x1,
    DWUART_DR_POS = 0,
};

enum DWUART_MSR_FIELD
{
    DWUART_DCD_MASK = 0x80,
    DWUART_DCD_POS = 7,
    DWUART_RI_MASK = 0x40,
    DWUART_RI_POS = 6,
    DWUART_DSR_MASK = 0x20,
    DWUART_DSR_POS = 5,
    DWUART_CTS_MASK = 0x10,
    DWUART_CTS_POS = 4,
    DWUART_DDCD_MASK = 0x8,
    DWUART_DDCD_POS = 3,
    DWUART_TERI_MASK = 0x4,
    DWUART_TERI_POS = 2,
    DWUART_DDSR_MASK = 0x2,
    DWUART_DDSR_POS = 1,
    DWUART_DCTS_MASK = 0x1,
    DWUART_DCTS_POS = 0,
};

enum DWUART_SCR_FIELD
{
    DWUART_SCRATCHPAD_MASK = 0xff,
    DWUART_SCRATCHPAD_POS = 0,
};

enum DWUART_LPDLL_FIELD
{
    DWUART_LPDLL_MASK = 0xff,
    DWUART_LPDLL_POS = 0,
};

enum DWUART_LPDLH_FIELD
{
    DWUART_LPDLH_MASK = 0xff,
    DWUART_LPDLH_POS = 0,
};

enum DWUART_SRBR0_STHR0_FIELD
{
    DWUART_SRBR0_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR0_MSB_9THBIT_POS = 8,
    DWUART_SRBR0_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR0_LSB_8BITS_POS = 0,
    DWUART_STHR0_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR0_MSB_9THBIT_POS = 8,
    DWUART_STHR0_LSB_8BITS_MASK = 0xff,
    DWUART_STHR0_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR1_STHR1_FIELD
{
    DWUART_SRBR1_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR1_MSB_9THBIT_POS = 8,
    DWUART_SRBR1_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR1_LSB_8BITS_POS = 0,
    DWUART_STHR1_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR1_MSB_9THBIT_POS = 8,
    DWUART_STHR1_LSB_8BITS_MASK = 0xff,
    DWUART_STHR1_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR2_STHR2_FIELD
{
    DWUART_SRBR2_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR2_MSB_9THBIT_POS = 8,
    DWUART_SRBR2_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR2_LSB_8BITS_POS = 0,
    DWUART_STHR2_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR2_MSB_9THBIT_POS = 8,
    DWUART_STHR2_LSB_8BITS_MASK = 0xff,
    DWUART_STHR2_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR3_STHR3_FIELD
{
    DWUART_SRBR3_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR3_MSB_9THBIT_POS = 8,
    DWUART_SRBR3_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR3_LSB_8BITS_POS = 0,
    DWUART_STHR3_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR3_MSB_9THBIT_POS = 8,
    DWUART_STHR3_LSB_8BITS_MASK = 0xff,
    DWUART_STHR3_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR4_STHR4_FIELD
{
    DWUART_SRBR4_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR4_MSB_9THBIT_POS = 8,
    DWUART_SRBR4_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR4_LSB_8BITS_POS = 0,
    DWUART_STHR4_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR4_MSB_9THBIT_POS = 8,
    DWUART_STHR4_LSB_8BITS_MASK = 0xff,
    DWUART_STHR4_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR5_STHR5_FIELD
{
    DWUART_SRBR5_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR5_MSB_9THBIT_POS = 8,
    DWUART_SRBR5_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR5_LSB_8BITS_POS = 0,
    DWUART_STHR5_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR5_MSB_9THBIT_POS = 8,
    DWUART_STHR5_LSB_8BITS_MASK = 0xff,
    DWUART_STHR5_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR6_STHR6_FIELD
{
    DWUART_SRBR6_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR6_MSB_9THBIT_POS = 8,
    DWUART_SRBR6_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR6_LSB_8BITS_POS = 0,
    DWUART_STHR6_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR6_MSB_9THBIT_POS = 8,
    DWUART_STHR6_LSB_8BITS_MASK = 0xff,
    DWUART_STHR6_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR7_STHR7_FIELD
{
    DWUART_SRBR7_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR7_MSB_9THBIT_POS = 8,
    DWUART_SRBR7_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR7_LSB_8BITS_POS = 0,
    DWUART_STHR7_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR7_MSB_9THBIT_POS = 8,
    DWUART_STHR7_LSB_8BITS_MASK = 0xff,
    DWUART_STHR7_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR8_STHR8_FIELD
{
    DWUART_SRBR8_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR8_MSB_9THBIT_POS = 8,
    DWUART_SRBR8_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR8_LSB_8BITS_POS = 0,
    DWUART_STHR8_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR8_MSB_9THBIT_POS = 8,
    DWUART_STHR8_LSB_8BITS_MASK = 0xff,
    DWUART_STHR8_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR9_STHR9_FIELD
{
    DWUART_SRBR9_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR9_MSB_9THBIT_POS = 8,
    DWUART_SRBR9_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR9_LSB_8BITS_POS = 0,
    DWUART_STHR9_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR9_MSB_9THBIT_POS = 8,
    DWUART_STHR9_LSB_8BITS_MASK = 0xff,
    DWUART_STHR9_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR10_STHR10_FIELD
{
    DWUART_SRBR10_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR10_MSB_9THBIT_POS = 8,
    DWUART_SRBR10_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR10_LSB_8BITS_POS = 0,
    DWUART_STHR10_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR10_MSB_9THBIT_POS = 8,
    DWUART_STHR10_LSB_8BITS_MASK = 0xff,
    DWUART_STHR10_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR11_STHR11_FIELD
{
    DWUART_SRBR11_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR11_MSB_9THBIT_POS = 8,
    DWUART_SRBR11_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR11_LSB_8BITS_POS = 0,
    DWUART_STHR11_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR11_MSB_9THBIT_POS = 8,
    DWUART_STHR11_LSB_8BITS_MASK = 0xff,
    DWUART_STHR11_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR12_STHR12_FIELD
{
    DWUART_SRBR12_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR12_MSB_9THBIT_POS = 8,
    DWUART_SRBR12_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR12_LSB_8BITS_POS = 0,
    DWUART_STHR12_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR12_MSB_9THBIT_POS = 8,
    DWUART_STHR12_LSB_8BITS_MASK = 0xff,
    DWUART_STHR12_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR13_STHR13_FIELD
{
    DWUART_SRBR13_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR13_MSB_9THBIT_POS = 8,
    DWUART_SRBR13_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR13_LSB_8BITS_POS = 0,
    DWUART_STHR13_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR13_MSB_9THBIT_POS = 8,
    DWUART_STHR13_LSB_8BITS_MASK = 0xff,
    DWUART_STHR13_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR14_STHR14_FIELD
{
    DWUART_SRBR14_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR14_MSB_9THBIT_POS = 8,
    DWUART_SRBR14_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR14_LSB_8BITS_POS = 0,
    DWUART_STHR14_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR14_MSB_9THBIT_POS = 8,
    DWUART_STHR14_LSB_8BITS_MASK = 0xff,
    DWUART_STHR14_LSB_8BITS_POS = 0,
};

enum DWUART_SRBR15_STHR15_FIELD
{
    DWUART_SRBR15_MSB_9THBIT_MASK = 0x100,
    DWUART_SRBR15_MSB_9THBIT_POS = 8,
    DWUART_SRBR15_LSB_8BITS_MASK = 0xff,
    DWUART_SRBR15_LSB_8BITS_POS = 0,
    DWUART_STHR15_MSB_9THBIT_MASK = 0x100,
    DWUART_STHR15_MSB_9THBIT_POS = 8,
    DWUART_STHR15_LSB_8BITS_MASK = 0xff,
    DWUART_STHR15_LSB_8BITS_POS = 0,
};

enum DWUART_FAR_FIELD
{
    DWUART_FIFO_ACCESS_MODE_MASK = 0x1,
    DWUART_FIFO_ACCESS_MODE_POS = 0,
};

enum DWUART_TFR_FIELD
{
    DWUART_TRANSMIT_FIFO_READ_MASK = 0xff,
    DWUART_TRANSMIT_FIFO_READ_POS = 0,
};

enum DWUART_RFW_FIELD
{
    DWUART_RFFE_MASK = 0x200,
    DWUART_RFFE_POS = 9,
    DWUART_RFPE_MASK = 0x100,
    DWUART_RFPE_POS = 8,
    DWUART_RFWD_MASK = 0xff,
    DWUART_RFWD_POS = 0,
};

enum DWUART_USR_FIELD
{
    DWUART_RFF_MASK = 0x10,
    DWUART_RFF_POS = 4,
    DWUART_RFNE_MASK = 0x8,
    DWUART_RFNE_POS = 3,
    DWUART_TFE_MASK = 0x4,
    DWUART_TFE_POS = 2,
    DWUART_TFNF_MASK = 0x2,
    DWUART_TFNF_POS = 1,
    DWUART_BUSY_MASK = 0x1,
    DWUART_BUSY_POS = 0,
};

enum DWUART_TFL_FIELD
{
    DWUART_TRANSMIT_FIFO_LEVEL_MASK = 0xffff,
    DWUART_TRANSMIT_FIFO_LEVEL_POS = 0,
};

enum DWUART_RFL_FIELD
{
    DWUART_RECEIVE_FIFO_LEVEL_MASK = 0xffff,
    DWUART_RECEIVE_FIFO_LEVEL_POS = 0,
};

enum DWUART_SRR_FIELD
{
    DWUART_XFR_MASK = 0x4,
    DWUART_XFR_POS = 2,
    DWUART_RFR_MASK = 0x2,
    DWUART_RFR_POS = 1,
    DWUART_UR_MASK = 0x1,
    DWUART_UR_POS = 0,
};

enum DWUART_HTX_FIELD
{
    DWUART_HALT_TX_MASK = 0x1,
    DWUART_HALT_TX_POS = 0,
};

enum DWUART_DMASA_FIELD
{
    DWUART_DMASA_MASK = 0x1,
    DWUART_DMASA_POS = 0,
};

enum DWUART_CPR_FIELD
{
    DWUART_FIFO_MODE_MASK = 0xff0000,
    DWUART_FIFO_MODE_POS = 16,
    DWUART_DMA_EXTRA_MASK = 0x2000,
    DWUART_DMA_EXTRA_POS = 13,
    DWUART_DWUART_ADD_ENCODED_PARAMS_MASK = 0x1000,
    DWUART_DWUART_ADD_ENCODED_PARAMS_POS = 12,
    DWUART_SHADOW_MASK = 0x800,
    DWUART_SHADOW_POS = 11,
    DWUART_FIFO_STAT_MASK = 0x400,
    DWUART_FIFO_STAT_POS = 10,
    DWUART_FIFO_ACCESS_MASK = 0x200,
    DWUART_FIFO_ACCESS_POS = 9,
    DWUART_NEW_FEAT_MASK = 0x100,
    DWUART_NEW_FEAT_POS = 8,
    DWUART_SIR_LP_MODE_MASK = 0x80,
    DWUART_SIR_LP_MODE_POS = 7,
    DWUART_SIR_MODE_MASK = 0x40,
    DWUART_SIR_MODE_POS = 6,
    DWUART_THRE_MODE_MASK = 0x20,
    DWUART_THRE_MODE_POS = 5,
    DWUART_AFCE_MODE_MASK = 0x10,
    DWUART_AFCE_MODE_POS = 4,
    DWUART_APB_DATA_WIDTH_MASK = 0x3,
    DWUART_APB_DATA_WIDTH_POS = 0,
};

enum DWUART_UCV_FIELD
{
    DWUART_UART_COMPONENT_VERSION_MASK = (int)0xffffffffL,
    DWUART_UART_COMPONENT_VERSION_POS = 0,
};

#endif
